1. Field of the Invention
The present invention relates to metal oxide semiconductor (MOS) transistors and a method for manufacturing the same, and more particularly, to a MOS transistor having enhanced device characteristics and a method for manufacturing the same.
2. Background of Related Art
In general, a MOS transistor formed on a semiconductor substrate includes a source region and a drain region created by implanting impurity ions of a conductivity type opposite to that of the substrate, a selectively conductive channel region between the source region and the drain region, and a gate electrode formed on the substrate with a gate insulating film imposed between the gate and the substrate.
Conventionally, the gate electrode may be made of an N-type polysilicon, to which a large quantity of phosphorous is added. Alternatively, the gate electrode may be made of a polycide gate structure composed of a high refractory metal silicide and a polysilicon, in which the N-type polysilicon layer is in direct contact with the gate insulating film. Since the work function difference between the N-type substrate and the N-type polysilicon is small, the use of N-type polysilicon increases the negative value of the threshold voltage. Impurity ions may be implanted into the channel region for decreasing the absolute value of the threshold voltage. Such an arrangement results in a very shallow P-N junction, and the resulting device is referred to as a buried channel type P-channel MOS transistor.
As the channel length of a transistor is reduced, certain problems such as decreased threshold voltage, sub-threshold deterioration, and breakdown voltage deterioration may occur which did not occur at longer channel lengths. These short-channel effects are more likely to occur in a buried channel type P-channel MOS transistor than in a surface-channel type.
To reduce the adverse effects of a short channel it has been proposed to form a surface-channel P-channel MOS transistor using P+ polysilicon for the gate electrode material. However, in this arrangement it is difficult to control the threshold voltage of the P-channel MOS transistor, due to the diffusion of boron ions in the P+ polysilicon layer into the channel region. It has also been proposed to form a P-channel MOS transistor similar to the surface-channel type by making the P-N junction depth in the channel region as shallow as possible. According to this proposal, the P-N junction depth of the channel region can be made shallow by implanting BF.sub.2, which is heavier than boron. However, this arrangement is susceptible to punchthrough; that is, when the drain-source voltage is high, the drain current is no longer controlled by the gate.
As the integration scale of semiconductor devices is increased, the transistor channel length is reduced and thus, methods to improve the short channel effects and prevent punchthrough of the P-channel MOS transistor are desirable.
To increase the voltage at which punchthrough occurs, it has been proposed to form a punchthrough stopper directly under the channel. According to this method, the impurity concentration under the channel is increased by implanting impurity ions of the same conductivity type as the substrate in a relatively high concentration. Such an arrangement suppresses punchthrough by preventing penetration of the drain electric field into the channel and source regions. The punchthrough stopper may be formed by a method where arsenic ions having a low diffusion coefficient are deeply implanted (IEEE transaction on Electron Device, VOL.ED-31, JULY, 1984, "Device Design for the Submicrometer p-Channel FET with n+ Polysilicon Gate"). This method can suppress surface punchthrough. However, it is difficult to suppress bulk punchthrough. In addition, if arsenic ions are implanted in a high concentration for suppressing bulk punchthrough, the silicon substrate is damaged due to the large mass of arsenic, and leakage current is increased.
Alternatively, a punchthrough stopper may be formed by an antipunchthrough ion implantation method where phosphorous ions are deeply implanted with high concentration (IEDM Technical Digest, 1987, "Submicron Short Channel Effects due to Gate Reoxidation Induced Lateral Interstitial Diffusion"). However, according to this method, phosphorous ions may be diffused into the surface of the channel, making it difficult to control the impurity distribution. Therefore, the majority carriers of the P-type channel region are compensated due to the N-type impurity, and thus, the threshold voltage is increased and the current driving ability of the device is reduced.